The present invention relates to a thin-film transistor used for driving an image sensor, electroluminescence display, liquid crystal display and the like, and more particularly to an improvement which can reduce variation of the on-current and off-current among individual thin-film transistors fabricated, and also can reduce a level of the off-current.
As a thin-film transistor of the above kind, there has been known one whose main part consists of, as shown in FIGS. 9-11, a glass substrate (a), a gate electrode (b) formed on the glass substrate (a), a gate insulating layer (c) covering the gate electrode (b), a first amorphous semiconductor layer (d) deposited on the gate insulating layer (c), a protective film (e) provide, as required, on the first amorphous semiconductor layer (d) and at the area corresponding to the gate electrode for protecting the first amorphous semiconductor layer (d), a second amorphous semiconductor layer (f) for ohmic contact containing trivalent or pentavalent impurity atoms and formed on the first amorphous semiconductor layer (d), source/drain electrodes (g), (h) electrically connected to the second amorphous semiconductor layer (f), and a diffusion preventive layer (j) for preventing the diffusion of the metal constituting the source/drain electrodes (g), (h) into the second amorphous semiconductor layer (f).
The conventional thin-film transistor of the above kind is fabricated through various steps as shown in FIG. 12(A) to FIG. 12(L).
Namely, as shown in FIGS. 12(A) and 12(B), on a glass substrate (a) with a gate electrode (b) formed thereon, there are deposited sequentially an SiN.sub.x insulating coating (c') which is to become the gate insulating layer (c), an amorphous silicon (a-Si) semiconductor coating (d') which is to become the first amorphous semiconductor layer (d), and an SiN.sub.x protective coating (e') which is to become the protective layer (e). Then the protective layer (e) is formed by selectively removing the protective coating (e') by photoetching, as shown in FIG. 12(C).
Next, a second amorphous semiconductor layer forming film (f') made of amorphous silicon (a-Si) containing pentavalent phosphorus (P) atoms, and a diffusion preventive layer forming film (j') made of chromium (Cr) are deposited sequentially as shown in FIG. 12(D). After forming a patterned resist film (k.sub.1) on the diffusion preventive layer forming film (j') as shown in FIG. 12(E), an etching is performed using an etchant consisting of a mixture, for example, of ammonium cerium nitrate (IV) and perchloric acid to remove the portion of the diffusion preventive layer forming film (j') not being covered by the resist film (k.sub.1). Then, the resist film (k.sub.1) is removed to expose the diffusion preventive layer (j) as shown in FIG. 12(F).
After forming again a resist film (k.sub.2) in patterned form on the diffusion preventive layer (j) as shown in FIG. 12(G), the substrate is subjected to an etching treatment which uses, for example, a hydrofluoric acid/nitric acid type etchant to remove the portion of the second amorphous semiconductor layer forming film (f') not being covered by the resist film (k.sub.2) and the outer portion of the underlying amorphous silicon (a-Si) semiconductor coating (d'). Then, removing the resist film (k.sub.2), there appears the structure containing the second amorphous semiconductor layer (f) and the first amorphous semiconductor layer (d), as shown in FIG. 12(H).
Further, as shown in FIG. 12 (I), the gate insulating film (c) is formed by selectively removing the SiN.sub.x insulating coating (c') by photoetching. Then, a layer (gh) of metal such as aluminum (Al) for the source/drain electrodes is deposited uniformly all over the surface as shown in FIG. 12(J). After a patterned resist film (k.sub.3) is formed as shown in FIG. 12(K) on the metallic layer (gh), source/drain electrodes (g), (h) are formed by removing the portion of the metallic layer (gh) not being covered by the resist film (k.sub.3) by an etching treatment as shown in FIG. 12(L), obtaining a thin-film transistor.
Now, in the above conventional thin film transistor, when the position of the resist film (k.sub.3) is deviated to one side due to misalignment at the time of formation of the resist film (k.sub.3) on the metallic layer (gh), the source/drain electrodes (g), (h) are formed such that one end of the electrodes (g), (h) is extended toward the protective layer (e) or the center of the first amorphous semiconductor layer (d). As a result, one of the source/drain electrodes (g), (h) and the protective layer (e) or the first amorphous semiconductor layer (d) will be connected directly in a portion. This causes a problem that the on-current and off-current are varied among thin-film transistors obtained depending on the size of the connection portion.
The inventor considers based on his analysis that the above variations are due to the following reasons.
Namely, in the thin-film transistor with the protective layer (e) as shown in FIG. 14, when a voltage is applied between the source/drain electrodes (g) and (h), a channel serving as a current path is formed, depending upon the kind of material forming the protective layer (e), in the interface between the protective layer (e) and the first amorphous semiconductor layer (d) due to the electric field, and electrons may be trapped by the protective film (e). When there is a variation in the size of the connection portion between the source/drain electrodes (g), (h) and the protective film (e), the number of electrons trapped by the protective film (e) is varied accordingly, so that there is produced a variation in the current flowing through the first amorphous semiconductor layer (d) among thin-film transistors fabricated.
On the other hand, in the case of the thin-film transistor without the protective layer as illustrated in FIG. 15, if there is a variation in the size of the connection portion between the source/drain electrodes (g), (h) and the first amorphous semiconductor layer (d), the effective gate length (.alpha.) is changed and the number of electrons trapped by the first amorphous semiconductor layer (d) is varied. As a result, the current flowing through the first amorphous semiconductor layer (d) is varied, so that there is generated a variation in the on-current and off-current among individual thin-film transistors fabricated.
In the conventional thin-film transistor, there is adopted a protection method in which the exposed surface (see FIGS. 14 and 15) of the protective film (e) or the first amorphous semiconductor layer (d) is covered with an appropriate film (not shown).
However, air, water, or the like may infiltrate into the space between the exposed surface and the appropriate film during the covering process. When such an item is attached to the surface of the protective film (e) or the first amorphous semiconductor layer (d), it tends to cause a leak, so that there occurs a problem that the off-current of the thin-film transistor is increased.